This application relies for priority upon Korean Patent Application No. 2000-40215, filed on Jul. 13, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates generally to semiconductor devices, and more particularly to a flash memory device having the least number of pins assigned on a single chip for increasing testing speed at a wafer level.
Applications of a flash memory have been extended because of the excellent operating speed and integration relative to other nonvolatile memory devices. In a memory cell formed of source and drain regions, a floating gate, and a control gate, various operations, such as programming, erasing, verifying, and reading, are performed. The programming injects an electron to the floating gate, and the erasing tunnels the electron from the floating gate to a channel region. As known in the art, varied testing operations are performed to identify the reliability of memory devices including the flash memory at a wafer level and at a package level. In general, one chip of a plurality of flash memory chips in a single wafer is tested at the wafer level, which causes an increasing time for the test in accordance with the increased memory device density.
It is therefore an object of the present invention to provide a flash memory device for decreasing a testing time. It is another object of the invention to provide a device for testing more flash memories in shorter time at wafer level.
It is still another object of the invention to a method for testing more flash memories in shorter time at wafer level.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having the least number of pins assigned on a single chip to test the maximum number of chips in a wafer at a time.
The semiconductor memory device in the present invention, includes an address counter generating a plurality of address signals in response to a signal provided from the outside, an address selection circuit controlling a path of the address signals, a plurality of switches divided in a predetermined number of groups and connected between a memory array and data input/output pins, and a switch control circuit generating switch control signals to control a switching operation of the switch groups in response to the external input signal. A portion of the data input/output pins is employed in correspondence with the number of the switch groups.
According to another aspect of this invention, there is provided a semiconductor device including a plurality of memory chips formed in a single wafer, each memory chip being connected to a source voltage pin, an earth voltage pin, a predetermined number of control signal pins, a test enable signal pin, a clock signal pin, and a portion of a plurality of data input/output pins. The respective memory chips include an input/output counter generating a plurality of counting signals in response to a test enable signal and a clock signal, an address counter generating a plurality of address signals in response to a counting signal, an address selection circuit controlling a path of the address signals, a plurality of switches divided into a predetermined number of switch groups and connected between a memory array and the data input/output pins, and a switch control circuit generating switch control signals to control a switching operation of the switch groups. The portion of the data input/output pins corresponds to the number of the switch groups.
According to the semiconductor device of the invention, it is possible to be applied to a write-in test as well as a read-out test, because the switches are bi-directionally operable.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings.